The present invention relates generally to multiplexing addresses and data at a memory interface, and more specifically to multiplexing address and data information to support multiple datapath widths with a single memory interface design.
In conventional computer systems, it has been common to use a device known as a Northbridge to handle data transfers between a central processing unit (CPU) and a system or main memory. The datapath between the Northbridge and the main memory has conventionally been 64 bits in width.
Recent improvements to this architecture have involved replacing the Northbridge with an integrated graphics processor (IGP), for example, an nForce™2 IGP by NVIDIA Corporation of Santa Clara, Calif. This IGP, like its Northbridge predecessor, communicates with both the CPU and main memory.
One of the improvements the nForce2 IGP provides over a conventional Northbridge is a wider 128-bit data path. This wider datapath reduces the bottleneck that occurs at the main memory in conventional computer systems. While this 128-bit data bus provides greatly improved performance over conventional 64-bit buses, it is desirable to provide devices having both 128-bit and 64-bit data buses to the marketplace. In this way, an array of products having different levels of performance at different price points can be offered by motherboard manufacturers.
Development costs for each motherboard are typically quite high, and can currently be on the order of $1 Million. Thus, it is very desirable to use one board design for both 64 and 128-bit modes of operation. Similar concerns exist for integrated circuit manufacturers, in that each new device must be separately tested, stocked, shipped, and inventoried.
Thus, what is needed are circuits, methods, and apparatus for memory interfaces that can support both a 64 and 128-bit datapath without changing the motherboard design. Further, it is preferable that one integrated circuit support both modes.